1. Field of the Invention
This invention relates to an IC card having a circuit for outputting attribute information (for example, the type, capacity, and access time) of the IC card memory.
2. Description of the Related Art
FIG. 4 is a block diagram showing an internal structure of a prior art IC card that employs read only semiconductor memories (hereafter ROMs). A mode control signal on a line 21 and a card enable signal on a line 22, connected through a connector 1, are supplied to a mode control circuit 2. One of the outputs of the mode control circuit 2 is a memory enable signal applied to a line 23. The memory enable signal line 23 is input to an address decoder 3 and a data output buffer 9. The address decoder 3 and an address input buffer 8 are provided with an address signal on a bus 26 via the connector 1. The address decoder 3 outputs a chip enable signal to a bus 25 to actuate one of ROMs 4 to 7. A post-buffer address signal. 27 is input from the address input buffer 8 to the ROMs 4 to 7. A data signal on a bus 28 or an output of the ROMs 4 to 7 is provided as a data signal on a bus 29 to the connector 1 via the data output buffer 9. The data signals on the buses 28 and 29, address signals on buses 26, 26a, and 27, and chip enable signal on bus 25 are parallel signals which are, therefore, transmitted over a data bus, an address bus, and a signal bus, respectively.
Another output of the mode control circuit 2 is an attribute output buffer enable signal 24. This signal is input to an attribute output buffer 11. Respective pull-up and pull-down resistors for each of the pins are connected to the attribute output buffer 11 that is used to set attribute information. An attribute data signal on bus 30 for transmitting attribute information is output as a data signal on bus 29 to the connector 1 via the attribute output buffer 11.
A mode control circuit 2 is controlled by two input signals, a mode control signal on line 21 and a card enable signal on line 22. When the card enable signal is high, regardless of the level of the mode control signal, a memory enable signal on line 23 does not actuate an address decoder 3 and a data output buffer 9. Moreover, an attribute output buffer enable signal on line 24 does not actuate an attribute output buffer 11. Hereinafter, when a signal does not actuate a circuit, the signal is called inactive. When a signal actuates a circuit means, the signal is called active. When the card enable signal is low, if the mode control signal is high, the memory enable signal becomes active and the attribute output buffer enable signal becomes inactive. When the card enable signal is low, if the mode control signal is also low, the attribute output buffer enable signal becomes active and the memory enable signal becomes inactive.
Therefore, this kind of IC card has three output states.
(A) Standby state
In this state, both the memory enable signal and an attribute output buffer enable signal are inactive. The address decoder 3, ROMs 4 to 7 connected to the address decoder 3, the data output buffer 9, and the attribute output buffer 11 are not actuated. The data signal on bus 29 has a high impedance. To attain this state, the card enable signal must be high.
(B) ROM read state
This is a state in which data is read out from ROMs. A memory enable signal is active, and the address decoder 3 and the data output buffer 9 are actuated. However, the attribute buffer 11 is not actuated. At this time, any one of ROMs 4 to 7 is selected according to the upper-level address 26a of an address signal on the bus 26 actuated by a chip enable signal on the bus 25. Data accessed according to the lower-level address is read out, placed on a data signal on the bus 28, and output as a data signal on the bus 29 to the connector 1 via the data output buffer 9. To attain this state, the card enable signal must be low, and a mode control signal high. At this time, since the attribute output buffer 11 is not actuated, its output has a high impedance and, therefore, does not interrupt data reading from the ROMs.
(C) Attribute output data read state
This is a state in which attribute information is read out. The address decoder 3 and the data output buffer 9 are not actuated, the attribute output enable signal is active,and the attribute output buffer 11 is actuated. At this time, all of the ROMs 4 to 7 are not actuated but are held at a high impedance. The levels set by the pull-up and pull-down down resistors included in the attribute information generator circuit 10 are read out as attribute output data and placed on the data signal bus 29. To attain this state, the card enable signal must be low, and the mode control signal must also be low.
The address input buffer 8 and the data output buffer 9 are indispensable for reducing the load across the connector 1 and thereby improving the interface characteristic of the connector 1.
FIG. 5 is a circuit diagram showing section B of FIG. 4 more specifically. In FIG. 5, sections C and D and part of the functions of an address decoder form a mode control circuit 2.
FIG. 6 is a block diagram showing the internal structure of an IC card disclosed in Japanese Patent Publication 63-237191. In FIG. 6, an access request signal line 50, an address select signal 51, and a write data line 52 from an upper-level unit handling a memory IC card are connected to a control circuit 53. The control circuit 53 controls all components in the memory IC card and provides a memory device array 54, an attribute signal setting circuit 55, and an attribute signal control circuit 56 with respective control signals 57 and 59. The memory device array 54 outputs read data on line 59. Upon switching of the switches, the attribute signal setting circuit 55 sets a signal for indicating the attribute of the memory IC card and then transmits the set signal on a line 58 to the attribute signal control circuit 56. The attribute signal control circuit 56 controls various kinds of attribute signals. Then, the output signal is transferred to the upper-level unit on line 60.
Prior art IC cards having the aforesaid configuration have several problems. For example, in the first described prior art card, an output buffer for reading data out of ROMs is incorporated independently of an attribute output buffer for reading out attribute output data. In the second described prior art card, an output channel of a memory device array is provided separately from an output channel for an attribute signal setting circuit and an attribute signal control circuit which is thought to include an attribute output buffer. Thus, both the first and second prior art structures include a large number of components. This results in a complex circuit configuration for an IC card and thereby reduces the reliability of the IC card.